In a liquid crystal display apparatus, (i) which includes a switch provided in every source line via which a signal (video signal) from a signal line is to be written, and (ii) which carries out a point-at-a-time driving with respect to each pixel, a method for simultaneously supplying signals of two or more channels is adopted so as to lower a driving frequency of the source line.
FIG. 5 is a block diagram illustrating a conventional liquid crystal display apparatus in which signals (video signals) that are supplied via two independent signal channels are supplied to the source lines via sampling switches, and the point-at-a-time drive is carried out.
As shown in FIG. 5, a display section 195 of the liquid crystal display apparatus includes a gate driver 185, a timing signal generating circuit 177, and a shift register 170 having output stages SiR155 and SiR156. The timing signal generating circuit 177 outputs a start pulse HST10. In response to the start pulse HST10, the output stages SiR155 and SiR156 output sampling pulses Vh20.
Then, in response to the sampling pulses Vh20, signals of two independent channels (a-channel and b-channel) are outputted. Specifically, the a-channel signals that respectively correspond to R (red), G (green), and B (blue) are sent to signal lines SLRa149 through SLBa151, respectively. Also, the b-channel signals that respectively correspond to R, G, and B are sent to signal lines SLRb152 through SLBa154, respectively.
Further, in the display section 195, a plurality of gate lines G190, G191, . . . , and the source lines SR101 through SB112 are wired in a matrix manner. For example, the gate line G191 intersects with the source lines SR101 through SB112, respectively, and in their intersections, thin film transistors TR125 through TB136 serving as a switching element are provided, respectively.
The thin film transistors TR125 through TB136 have (i) respective gates connected to the gate line G191, and (ii) sources connected to the source lines SR101 through SB112, respectively, and (iii) drains connected to the pixel capacitance PR113 through PB124, respectively. The source lines SR101 through SB112 are divided into four groups Gr154, Gr155, Gr156, and Gr157 so that each group is constituted by three source lines (that correspond to one pixel). The groups Gr154, Gr155, Gr156, and Gr157 are further divided into two blocks B158 and B159 so that each block is constituted by two groups (that correspond to two pixels) adjacent to each other.
Furthermore, the source lines SR101 through SB112 are connected to the signal lines SLRa149 through SLBb154, via sampling switches SWR137 through SWB148, respectively. The sampling switches SWR137 through SWB148 may be realized by transistors, respectively, and are provided so as to correspond to the source lines SR101 through SB112, respectively.
Specifically, in the group Gr154, the three source lines SR101, SG102, and SB103 are connected to the a-channel signal lines SLRa149, SLGa150, and SLBa151, via the sampling switches SWR137, SWG138, and the SWB139, respectively. Also, in the group Gr155, the three source lines SR104, SG105, and SB106 are connected to the b-channel signal lines SLRb152, SLGb153, and SLBb154, via the sampling switches SWR140, SWG141, and the SWB142, respectively. The groups Gr154 (the a-channel) and Gr155 (the b-channel), which are adjacent to each other, constitute the block B158.
Here, each of the six sampling switches SWR137 through SWB142 in the block B158 is connected to the output stage SiR155 of the shift register 170, and each ON/OFF of the six sampling switches SWR137 through SWB142 is controlled in response to the sampling pulse Vh20 outputted from the output stage SiR155. Further, in response to the sampling pulses Vh20, the signals of the two channels are sent from the respective signal lines (the a-channel: SLRa149 through SLBa151; the b-channel: SLRb152 through SLBb154).
Similarly, in the group Gr156, the three source lines SR107, SG108, and SB109 are connected to the a-channel signal lines SLRa149, SLGa150, and SLBa151, via the sampling switches SWR143, SWG144, and SWB145, respectively. Further, in the group Gr157, the three source lines SR110, SG111, and SB112 are connected to the b-channel signal lines SLRb152, SLGb153, and SLBb154, via the sampling switches SWR146, SWG147, and SWB148, respectively. The groups Gr156 (the a-channel) and Gr157 (the b-channel), which are adjacent to each other, constitute the block B159.
Here, each of the six sampling switches SWR143 through SWB148 of the block B159 is connected to the output stage SiR156 of the shift register 170, and each ON/OFF of the six sampling switches SWR143 through SWB148 is controlled in response to the sampling pulse Vh20 outputted from the output stage SiR156. Further, in response to the sampling pulses Vh20, the signals of the two systems are sent from the signal lines (the a-channel: SLRa149 through SLBa151; the b-channel: SLRb152 through SLBb154), respectively.
In the display section 195 thus arranged, while the gate line G190 or G191 is selected (turned ON) by the gate driver 185, the output stage SiR155 or SiR156 sends, at the same timing, the sampling pulses (selection signals) Vh20 to the sampling switches (such as the sampling switch 137) for every block (or for every group). Accordingly, the signals which are supplied via the signal lines (such as the signal line SLRa149) are written, via the source lines that correspond to the sampling switches, in the pixel capacitance (such as the pixel capacitance PR113), respectively.
Hereinafter, a conventional method for driving the display section 195 is described in detail with reference to FIG. 5 and FIG. 6.
FIG. 6 is a timing chart illustrating the twelve sampling switches SWR137 through SWB148 during an odd-numbered frame period and an even-numbered frame period, the switches SWR137 through SWB148 belonging to the block B158 or B159, each block corresponding to two pixels. FIG. 6 also illustrates electric potential states (writing states of the signals) of the respective twelve source lines SR101 through SB112 that belong to the block 158 or 159, and that correspond to four pixels.
Note that, in FIG. 6, indicated by a symbol T is a period (that corresponds to one cycle of the timing signal) in which the signals are written in two pixels. Note also that the term “frame period” indicates time required for scanning all the gate lines G190, . . . , in the display section 195 (i.e., a period of time required for scanning one screen).
As shown in FIG. 6, in synchronization with a timing signal (not shown) outputted from the timing signal generating circuit 177, simultaneously selected (turned ON) at time t0 are the sampling switches SWR137 through SWB142 of the group Gr154 or Gr155, each group belonging to the block B158.
During a period of time from the time t0 to time t1, the signals which are supplied via the signal lines SLRa149 through SLBb154 are written, at the same timing, in the pixel capacitance PR113 through PB118, via the source lines SR101 through SB106 that are connected to the sampling switches SWR137 through SWB142, respectively.
Thereafter, at the time t1 that is one clock (cycle) after the time t0, a timing signal (not shown) is outputted. In synchronization with the timing signal, (i) simultaneously turned OFF are the sampling switches SWR137 through SWB142 of the group Gr154 or Gr155, each group belonging to the block B158, and (ii) simultaneously selected (turned ON) are the sampling switches SWR143 through SWB148 of the group Gr156 or Gr157, each belonging to the block B 159.
During a period of time from the time t1 to time t2, the signals which are supplied via the signal lines SLRa149 through SLBb154 are written, at the same timing, in the pixel capacitance PR119 through PB124, via the source lines SR107 through SB112 that are connected to the sampling switches SWR143 through SWB148, respectively.
However, according to the method for driving the display section 195, the source line SB106 (edge source line in the block B158) followed by the adjacent block B159 changes in its electric potential due to a parasitic capacitance between the source lines SB106 and SR107 (i.e., electric charge of the parasitic capacitance transfers to (jumps into) the source line SB106). Similarly, the source line SB112 changes in its electric potential due to parasitic capacitance between the source lines SB112 and SR161. This gives rise to the changes in electric potential which has been written in the pixel capacitance PB118 and PB124. These changes arise the problems to be solved.
FIG. 7 schematically shows the parasitic capacitance C201 and C202, the parasitic capacitance C201 existing between the source line SR107 and the source line SB106 (an electrode on a side of the source line of the pixel capacitance PB118), and the parasitic capacitance C202 existing between the source lines SB112 and SR161.
For example, as for the source lines SB106 and SR107, because the sampling switch SWB142 belonging to the block B158 is turned ON at the time t0, the source line SB106 connected to the sampling switch SWB142 receives the signal (electric potential) via the signal line SLBb154 during the period of time from the time t0 to the time t1. Meanwhile, during the period of time from the time t0 to the time t1, the sampling switch SWR143 which belongs to the block B159 adjacent to the block B158 is turned OFF. This causes the source line SR107 connected to the sampling switch SWR143 to keep electric potential which was given one horizontal period ago. Thus, an electric potential difference becomes large between the source line SR107 and the source line SB106 (the electrode on the side of the pixel capacitance PB118) and, the source line SB106 receiving a new current signal (electric potential), whereas the source line SR107 keeping the electric potential which was given one horizontal period ago. This causes the large parasitic capacitance (accumulation of electric charge; see C201 in FIG. 7) between the source lines SB106 and SR107.
When the sampling switch SWR143 is turned ON at the time t1 so that a new signal (electric potential) is given to the source line SR107 connected to the sampling switch SWR143, the electric potential difference between the source line SR106 and the source line SR107 (an electrode on a side of the pixel capacitance PR119) is reduced. Accordingly, electric charge accumulated in the parasitic capacitance C201 transfers to (jumps into) the source line SB106, thereby changing the electric potential of the source line SB106.
Similarly, at the time t2, electric charge of the parasitic capacitance C202 (accumulation of electric charge; see C202 in FIG. 7) between the source line SB112 and a source line SR161, transfers to (jumps into) the source line SB112, thereby changing the electric potential of the source line SB112.
FIG. 6 schematically shows (i) the change in electric potential of the source line SB106 from the time t1 on, and (ii) the change in electric potential of the source line SB112 from the time t2 on (see the electric potential change indicated by the arrows in FIG. 6).
Thus, when simultaneously selecting all the groups in one block—for example, the groups Gr154 and Gr155 in the block B158, or the groups Gr156 and Gr157 in the block B159—during the odd-numbered frame period or the even-numbered frame period, parasitic capacitance (such as the parasitic capacitance C201 or C202) occurs between two source lines (like between the source lines SB106 and SR107, or between the source lines SB112 and SR161) which belong to respective different groups, and which are disposed at a “boundary” between the groups adjacent to each other such as the groups Gr155 and Gr156. The parasitic capacitance causes the changes in electric potential of end portions of the source lines (SB106 and SB112), each of the end portions being opposite to a selection direction (i.e., a direction in which the sampling switches shift).
This causes the display section 195 to have display unevenness, in a vertical-striped manner, which is enhanced for every block (for the block B158, and for the block B159), i.e., for every six source lines or for every two pixels.